A critical element of today's faster, more powerful computers is the silicon semiconductor chip which provides the computer its logic or processing power. Commonly, a number of chips are mounted together on a ceramic or silicon substrate. In this form, they are referred to as modules.
The fabrication of a computer chip is a complex operation requiring skill in both the chip design and chip manufacture. This is no less true for the module. On a very simplistic level, the manufacture of the module is as follows. Once the single chips are diced from wafers, they are soldered (using solder bumps or "C4s") to metal pads on a silicon substrate. The silicon substrate is joined to a ceramic carrier with an adhesive. (The silicon substrate and ceramic carrier will together be referred to as the substrate.) Wire bonds made of fine wire are bonded between the aluminum contact pads on the chips and gold plated pads on the substrate that make contact with external pins (or leads). A cover or lid is then sealed over the chips to the surface of the substrate. FIG. 1 illustrates a specific module, namely a VCOS module, prior to lid sealing. As can be seen from this figure, the wire bonds (4) connect to gold leads (6) which are held in place by a lead frame (8) during the sealing operation in which the cover or lid (14) is sealed into place. The lid 14 is shown twice in FIG. 1, in both inverted and upright orientations, for illustration (e.g., of solder placement) purposes.
Due to the large number of steps in the process and the difficulty of each process step, only a fraction will be fully functional. The yield of a process is the fraction of modules fabricated that do not contain flaws. Higher yields are desirable: as the yield improves, more useful modules are produced from a given amount of resources and profits increase.
One of the more sensitive steps in the process of module packaging--and one which can have significant impact on yield--is the step of sealing the lid over the substrate. One method used in this sealing is to create a sealband (10) on the upper surface of the substrate (12). (The term "upper surface" is used to refer to that surface of the substrate to which the chips are attached). The sealband is formed by impregnating the ceramic surface of the substrate with metal and electroplating a metal band (generally a layer of nickel followed by a layer of gold to prevent oxidation) on top of the impregnated area. As is illustrated in the figure, the sealband (10) is formed outside of the device area, that is, it does not contact the chips (1) or the wire bonds (4).
A solder preform (16) is then joined with flux to the lower surface of the lid in a similar profile to the sealband. That is, the solder is formed on the lid to form a pattern which is slightly smaller but otherwise generally matches the sealband area. (The "lower surface" of the lid refers to the surface which will be jointed to the substrate.) The lid is set into place on the substrate so that the sealband and lid with its solder attached are in contact. The entire package (lid, solder, and substrate with sealband) is heated. This causes the solder to melt and join the lid to the substrate. FIG. 2 is a schematic representation of a module with a substrate (2) and a lid (14) held together by solder. In the module illustrated, the substrate sealband is larger than the lid and much of the solder seal is visible (FIGS. 2, 19).
During the sealing process, as the solder is heated, it melts and becomes liquidus, spreading over a larger surface. If the solder spreads into the module, the result is referred to as a solder intrusion.
Solder intrusions are a familiar occurrence, although their exact cause can be difficult to determine. It has been suggested that some intrusions are caused by a pressure differential between the inside and the outside of the package. As the module cools after reflow, the temperature inside the module drops, causing a drop in pressure, which causes the solder to be sucked into the module.
Solder intrusions can cause a number of problems that can significantly impact the yield of a packaging process. First, the solder intrusions are connected to the grounded metal sealband (where the solder was originally placed). If the intrusion bridges between a wire bond area and the sealband, the intrusion can cause a short which will cause the package to fail testing.
The solder intrusions can also cause fine pinholes to form within the seal between the lid and the substrate. This will cause a less than gas-tight seal and the package must be reworked. (The measure of the number of packages which have acceptable seals is referred to as the hermeticity yield).
Finally, for those modules where the substrate sealband is larger than the lid (as illustrated in FIGS. 2, 19), poor flow to the outside of the module can cause an uneven spread of solder over the visible edge of the band. The unevenness cause concern in any visual inspection of the module, resulting a re-X-ray of the module to ensure that the seal was tight.
Solder intrusions have long been a known problem, however, in many types of processes they do not occur with any degree of frequency. It is known, however, that large modules with relatively large sealbands can experience significant solder intrusions. As a result, in VLSI technology, solder intrusions can present a significant problem.
Several techniques were used in the prior art to reduce intrusions.
One such technique was to regulate the temperature of the sealing process. This technique was based on the fact that large intrusions occurred if the temperature during lid seal rose above a specific peak. Thus, at high temperatures, extremely large yield losses on the order of 30% occurred. More specifically, approximately 30 out of each 100 modules would fail functional testing due to solder intrusions bridging to the wire bond pads. In addition, another one to 5 percent of the modules would fail the hermeticity test. Conversely, keeping the peak temperature below 285.degree. C. reduced intrusions and improved overall yields.
Unfortunately, the use of cooler temperatures did not provide a total solution. Intrusions were decreased in the quantity and size but were not eliminated: between 2 and 5 percent of the modules still experienced intrusion problems. In addition, if a temperature below 285.degree. C. was used, the solder did not flow well, causing hermeticity losses of one to two percent. Further, the solder flow to the outside edge was often uneven, resulting in the modules being submitted to additional testing or simply being rejected out of hand.
Another technique to reduce solder intrusions involved sealing the modules in a pressure vessel. Then, during the heating and cooling of the sealing process, the ambient pressure was periodically changed in order to prevent pressure differentials. This solution was expensive, in that it called for additional equipment (the pressure vessel) and additional process steps (namely, a continual monitoring and altering of the pressure). Further, unless the pressure was constantly monitored and altered so that the pressure inside and outside the module was kept approximately equal, solder intrusions would still form.
Still another means of dealing with the solder intrusion problem involves module design. Designs with more chips in the module generally experience fewer intrusions. Modules designed with no metallurgy close to the edges of the sealband experienced solder intrusions but will experience fewer shorts since many of the solder intrusions will not extend to the wire bonds.
Solving the problem with the module design is not, however, always feasible. Modules with a significant amount of complex function may not be able to give up use of the space adjoining the sealband: packaging chips in less space allows more functionality on a card.